This invention relates to the timing simulation of integrated circuits, and in particular, the construction of a end point report for a timing simulation.
When analyzing the timing report in order to find out whether the designed hardware fits into the clock cycle, the end point report is the best choice. But for larger designs that have aggressive timing goals like CPUs, a hierarchical design is often used to divide the design into handy pieces. But the timing report then ends at the border of these pieces and the other hierarchy components are abstracted using timing assertions.
This abstraction makes timing analysis cumbersome, due to either missing completeness for the lower hierarchy level, or missing details in the higher abstraction level.
End point reports for the lower hierarchy level (called macros) end at the abstraction border and thus become outdated together with the border values, which may change due to changes in other parts of the design. End point reports for the upper hierarchy level (called unit) offer correct and up-to-date timing results, but they do not reveal the design details of the lower hierarchy level, which also hides the root cause for bad timing data.
Also, the timing abstract assertions are created based on a previous timing run and thus do not reflect present reality, but the past. Timing data for the lower hierarchy level is based on these assertions and thus this timing data has the same deviations from present reality like the assertions it is based upon.